REG[9]

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Interpret as REG[9]

Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)

REG	At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0).

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